The notion of data prefetching in microprocessors is well known. The microprocessor observes the addresses of recent memory requests and attempts to predict which data will be needed in the future and prefetches the predicted data into a cache memory of the microprocessor in order to avoid the relatively long latency associated with an access to system memory required when a cache miss occurs. It is easy to predict data that will be needed in the future from observing a simple sequence of memory accesses. However, programs also access data in patterns that are more complex than a simple sequential pattern. Designing a data prefetcher to predict future-needed data for complex access patterns may require significant power and timing resources, thereby negatively affecting clock cycle lengths and power consumption of modern microprocessors, both of which are important concerns. Therefore, what is needed is an efficient data prefetcher for predicting complex access patterns.